发明名称 |
Operation Of I/O In A Safe System |
摘要 |
A module health system includes a module health circuit comprising a hardware register that is set to a first value in response to the system starting, an application register that is set to the first value in response to the system starting and a watchdog timer register that is set to the first value in response to the system starting. The system further includes a power on self-test that determines whether the system has passed a plurality of tests and that selectively sets the hardware register to a second value based on the determination, an external software application that determines whether a safety critical system is healthy and selectively sets the application register based on the determination, a watchdog timer application that selectively sets the watchdog timer register, a central processing unit that determines whether to de-assert a module health signal. |
申请公布号 |
US2015169424(A1) |
申请公布日期 |
2015.06.18 |
申请号 |
US201414219043 |
申请日期 |
2014.03.19 |
申请人 |
Emerson Network Power - Embedded Computing, Inc. |
发明人 |
VAANANEN Pasi Jukka Petteri;CORNES Martin Peter John;PRI-TAL Shlomo |
分类号 |
G06F11/30;G06F11/34;G06F11/22 |
主分类号 |
G06F11/30 |
代理机构 |
|
代理人 |
|
主权项 |
1. A module health system comprising:
a module health circuit that includes: a first hardware (HW) register that is set to a first value in response to the system starting; a first application register that is set to the first value in response to the system starting; a first watchdog (WD) timer register that is set to the first value in response to the system starting; a first power on self-test (POST) that determines whether the system has passed a plurality of tests and that selectively sets the first HW register to a second value based on the determination; an external software application that determines whether a safety critical system is healthy and selectively sets the first application register based on the determination; a watchdog timer application that selectively sets the first WD timer register in response to receiving a watchdog signal; and a first central processing unit (CPU) that determines whether to de-assert a first module health signal based on a value of the first HW register, the first application register, and the first WD timer register. |
地址 |
Tempe AZ US |