CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY

摘要

A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

主权项

1. An apparatus, comprising:
a synchronization circuit configured to receive a first clock signal, and provide a second clock signal based, at least in part, on the first clock signal; a mode register configured to store a latency value; and a latency control circuit coupled to the synchronization circuit and the mode register, the latency control circuit configured to receive the first clock signal, the second clock signal, the latency value, and a command signal, wherein the latency control circuit is further configured to latch the command signal responsive, at least in part, to the first clock signal to provide a latched command signal, hold the latched command signal for an amount of time based, at least in part, on the latency value, and provide the latched command signal responsive, at least in part, to the second clock signal.