DUAL PORT SRAM BITCELL STRUCTURES WITH IMPROVED TRANSISTOR ARRANGEMENT

摘要

Dual port static random access memory (SRAM) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors. The bitcell structures may also include pass-gate transistors PGLA and PGRA forming a first port, and pass-gate transistors PGLB and PGRB forming a second port. The pass-gate transistors PGLA and PGLB may be adjacent one another and a first side of the bitcell structure, and pass-gate transistors PGRA and PGRB may be adjacent one another and a second side of the bitcell structure. Each of the pass-gate transistors PGLA and PGLB may be connected with one of the pull-down transistors of one of the pairs of parallel pull-down transistors. Similarly, each of the pass-gate transistors PGRA and PGRB may be connected with one of the pull-down transistors of the other pair of parallel pull-down transistors.

主权项

1. A dual port static random access memory (SRAM) bitcell structure comprising:
a substantially rectangular cell area having a relatively longer dimension of the cell area extend between a first side of the bitcell structure to a second side of the bitcell structure; pass-gate transistors PGLA and PGRA forming a first port; pass-gate transistors PGLB and PGRB forming a second port; and a latch formed of pull-up transistors PUL and PUR and pull-down transistors PDR and PDL configured to store a bit, transistor PGLB being adjacent the first side of the bitcell structure, and transistor PGLA being adjacent transistor PGLB in a first direction extending from the first side to the second side of the bitcell structure, transistor PGRB being adjacent the second side of the bitcell structure, and transistor PGRA being adjacent transistor PGRB in a second direction extending from the second side to the first side of the bitcell structure, and pass-gate transistors PGLA, PGRA, PGLB and PGRB, pull-up transistors PUL and PUR and pull-down transistors PDR and PDL being formed on the same layer.