DOUBLE DATA RATE COUNTER, AND ANALOG-TO-DIGITAL CONVERTER AND CMOS SENSOR INCLUDING THE SAME

摘要

A double data rate (DDR) counter includes a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher; a third control block suitable for determining an enable period of the counting block; the sampling block suitable for sampling a state of the clock signal and outputting an LSB value, when an input signal transits; and the counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher.

主权项

1. A double data rate (DDR) counter comprising:
a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher; a third control block suitable for determining an enable period of the counting block; said sampling block suitable for sampling a state of the clock signal and outputting an LSB value when an input signal transits; and said counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher.