发明名称 |
MOS TRANSISTORS HAVING LOW OFFSET VALUES, ELECTRONIC DEVICES INCLUDING THE SAME, AND METHODS OF FABRICATING THE SAME |
摘要 |
A MOS transistor includes a gate electrode disposed over an active region without overlapping with an isolation region, the active region including a channel region, the isolation region defining the active region, a source region and a drain region disposed in first and second portions of the active region, respectively, the first and second portions being disposed at first and second sides of the gate electrode, respectively, the first side opposing the second side, a first blocking region disposed in a third portion of the active region between a third side of the gate electrode and the isolation region and between the source and the drain region, and a second blocking region disposed in a fourth portion of the active region between a fourth side of the gate electrode and the isolation region and between the source and the drain region, the fourth side opposing the third side. |
申请公布号 |
US2015171809(A1) |
申请公布日期 |
2015.06.18 |
申请号 |
US201414253493 |
申请日期 |
2014.04.15 |
申请人 |
SK HYNIX INC. |
发明人 |
SONG Hyun Min |
分类号 |
H03F3/45;H01L29/06;H01L29/423;H01L27/088 |
主分类号 |
H03F3/45 |
代理机构 |
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代理人 |
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主权项 |
1. A metal oxide semiconductor (MOS) transistor comprising:
a gate electrode disposed over an active region without overlapping with an isolation region, the active region including a channel region, the isolation region defining the active region; a source region and a drain region disposed in first and second portions of the active region, respectively, the first and second portions being disposed at first and second sides of the gate electrode, respectively, the first side opposing the second side; a first blocking region disposed in a third portion of the active region between a third side of the gate electrode and the isolation region and between the source region and the drain region; and a second blocking region disposed in a fourth portion of the active region between a fourth side of the gate electrode and the isolation region and between the source region and the drain region, the fourth side opposing the third side, wherein the source region and the drain region have a first conductivity type and the first and second blocking regions have a second conductivity type opposite to the first conductivity type. |
地址 |
Icheon KR |