| 发明名称 |
REDUCING POWER CONSUMPTION IN A PROCESSOR |
| 摘要 |
A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit. |
| 申请公布号 |
US2015169041(A1) |
申请公布日期 |
2015.06.18 |
| 申请号 |
US201314104042 |
申请日期 |
2013.12.12 |
| 申请人 |
Apple Inc. |
发明人 |
Blasco Conrado;Hall Ronald P.;Gunna Ramesh B.;Kountanis Ian D.;Sundar Shyam;Seznec André |
| 分类号 |
G06F1/32;G06F9/38 |
主分类号 |
G06F1/32 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor comprising:
a branch prediction unit including a memory array for storing conditional branch prediction information; and a next fetch prediction unit including a plurality of entries, each corresponding to a next instruction fetch group, wherein each entry stores an indication of whether or not the corresponding next fetch group includes a conditional branch instruction; wherein in response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit is configured to disable, in a next instruction execution cycle, the memory array. |
| 地址 |
Cupertino CA US |
