COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN

摘要

Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

主权项

1. A method, comprising:
generating a behavioral representation of a design for an integrated circuit, wherein the behavioral representation comprises a register transfer level (RTL) description of a 1×N building block; generating a physical design representation based on the behavioral representation, wherein the physical design representation comprises one of a flat netlist, a hierarchical netlist, and a partially flattened netlist; and generating, via a 1×N compiler, a logical representation via the physical design representation.