| 摘要 |
A self-adjusting delay circuit (1) adapted to delay a received clock signal (CLK) provided for a received data signal (data), said self-adjusting delay circuit (1) comprising a clock edge counter (4) adapted to count signal edges of the received clock signal (CLK) to provide an incremented n-bit counter value applied to an adjustable delay line (5) having a corresponding number (n) of inverters connected to each other in parallel and each inverter being enabled by an associated bit of said n-bit counter value to invert the received clock signal (CLK) with a driving current strength of the inverter corresponding to the significance of the respective bit of said n-bit counter value to load a capacitor (53) of said adjustable delay line (5), wherein the received clock signal (CLK) is delayed by said adjustable delay line (5) with an increasing time delay proportional to the incremented n-bit counter value output by said clock edge counter (4) until an edge comparator (8) detects that a rising signal edge of the received data signal (data) precedes a rising signal edge of the delayed clock signal (CLK') output by said adjustable delay line (5) including a time margin provided by a phase margin security circuit (12). |
