发明名称 自動利得制御ループ内の増幅器の少なくとも1つの入力信号を減衰させるためのユニットを有する電子回路
摘要 <p>The circuit (1) has an attenuation unit (10) including a comparison unit for comparing an adaptation signal (VAGC) to a reference signal (VREF) and for supplying an attenuation current, whose intensity is a function of difference between the adaptation and reference signals. A diode-connected replica transistor (M2) controls a shunt transistor (M1) having a conductivity type, which defines a shunt resistance connected to an input of an input amplifier (2) e.g. LNA amplifier. A resistive value of the input depends on the intensity of the current passing through the replica transistor.</p>
申请公布号 JP5735079(B2) 申请公布日期 2015.06.17
申请号 JP20130221974 申请日期 2013.10.25
申请人 发明人
分类号 H03G3/30;H03G3/20 主分类号 H03G3/30
代理机构 代理人
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