发明名称 正規化カウントを判定するプロセッサ及び方法
摘要 In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.
申请公布号 JP5735150(B2) 申请公布日期 2015.06.17
申请号 JP20140036985 申请日期 2014.02.27
申请人 发明人
分类号 G06F7/74;G06F9/30;G06F9/305 主分类号 G06F7/74
代理机构 代理人
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