发明名称 自己整合ローカル・インターコネクト・プロセスにおけるゲートへの選択的なローカル・インターコネクト
摘要 <p>A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.</p>
申请公布号 JP5735494(B2) 申请公布日期 2015.06.17
申请号 JP20120514025 申请日期 2010.06.01
申请人 发明人
分类号 H01L21/768;H01L23/522 主分类号 H01L21/768
代理机构 代理人
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