发明名称 NANDフラッシュメモリにおける階層的な共通ソース線構造
摘要 <p>Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.</p>
申请公布号 JP5736441(B2) 申请公布日期 2015.06.17
申请号 JP20130247005 申请日期 2013.11.29
申请人 发明人
分类号 G11C16/06;G11C16/02;G11C16/04 主分类号 G11C16/06
代理机构 代理人
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