Enhanced stress memorization technique for metal gate transistors

摘要

A method of manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor substrate, forming sidewall spacers, and forming heavily doped source/drain regions. After removing the spacers, a stress material layer is formed over the dummy gate structure. An annealing process is performed to transfer the stress to the device channel region. After the annealing process, the stress material layer is removed. The dummy gate structure is replaced by a high-k dielectric layer and a metal gate structure. Subsequently, contact holes are formed to expose at least part of the heavily doped source/drain regions, and self-aligned silicide is formed over exposed portions of the heavily doped source/drain regions.

主权项

1. A method of manufacturing a semiconductor device, comprising:
forming a dummy gate structure on a semiconductor substrate, the dummy gate structure including a sacrificial gate electrode layer over a sacrificial gate dielectric layer; forming sidewall spacers on both sides of the dummy gate structure; performing a deep pre-amorphization implant; performing an ion implantation to form heavily doped source/drain regions in the semiconductor substrate; removing the sidewall spacers; after removing the sidewall spacers, forming a stress material layer over the dummy gate structure; performing an annealing process; after the annealing process, removing the stress material layer; forming an interlayer dielectric layer surrounding the dummy gate structure; removing the dummy gate structure to form a groove in the interlayer dielectric layer; forming a high-k dielectric layer and a metal gate structure in the groove; forming contact holes that expose at least part of the heavily doped source/drain regions; and forming a self-aligned silicide over exposed portions of the heavily doped source/drain regions.