EEPROM

摘要

An EEPROM includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. First through fifth impurity regions are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, and first and second floating gates are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, first and second tunnel windows are respectively formed at portions in contact with the first and second floating gates. A sixth impurity region of the second conductive type, which is connected to the second impurity region, is formed in the top layer portion of the semiconductor layer that opposes the second tunnel window.

主权项

1. An EEPROM (electrically erasable programmable read only memory), comprising:
a semiconductor layer of a first conductive type; a first insulating film formed on the semiconductor layer; a first impurity region of a second conductive type formed in a top layer portion of the semiconductor layer; a second impurity region of the second conductive type formed at an interval from the first impurity region in a top layer portion of the semiconductor layer; a first select gate formed on the first insulating film and opposing a region between the first impurity region and the second impurity region; a third impurity region of the second conductive type formed at an interval from the second impurity region in a top layer portion of the semiconductor layer; a first floating gate formed on the first insulating film and opposing a region between the second impurity region and the third impurity region; a second insulating film formed on the first floating gate; a first control gate formed on the second insulating film; a first tunnel window formed by decreasing a thickness of a part of a portion of the first insulating film in contact with the first floating gate and sandwiched between the first floating gate and the second impurity region in a thickness direction of the first insulating film; a fourth impurity region of the second conductive type formed at an interval from the third impurity region in a top layer portion of the semiconductor layer; a second floating gate formed on the first insulating film and opposing a region between the third impurity region and the fourth impurity region; a third insulating film formed on the second floating gate; a second control gate formed on the third insulating film; a second tunnel window formed by decreasing a thickness of a part of a portion of the first insulating film in contact with the second floating gate and sandwiched between the second floating gate and the fourth impurity region in the thickness direction of the first insulating film; a fifth impurity region of the second conductive type formed at an interval from the fourth impurity region in a top layer portion of the semiconductor layer; and a second select gate formed on the first insulating film and opposing a region between the fourth impurity region and the fifth impurity region; wherein the first tunnel window is arranged closer to an edge of the first floating gate near the first select gate than to an edge of the first floating gate near the third impurity region; wherein the second tunnel window is arranged closer to an edge of the second floating gate near the second select gate than to an edge of the second floating gate near the third impurity region; and wherein a top surface of the third impurity region is not connected to a contact plug.