发明名称 |
Semiconductor device and driving method thereof |
摘要 |
A data saving period control circuit; a power gating control circuit; and a data processing circuit including a general-purpose register, an error correction code storage register, and an error correction code circuit are included. The general-purpose register and the error correction code storage register each include a volatile memory unit and a nonvolatile memory unit. The data saving period control circuit is a circuit for changing a length of a data saving period in which data output from the power gating control circuit is saved from the volatile memory unit to the nonvolatile memory unit included in the general-purpose register, depending on whether an error in an error correction code stored in the error correction code storage register is detected by the error correction code circuit. |
申请公布号 |
US9058867(B2) |
申请公布日期 |
2015.06.16 |
申请号 |
US201313900578 |
申请日期 |
2013.05.23 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Yoneda Seiichi |
分类号 |
G11C14/00;G06F1/30;G06F11/14;G06F11/10;G06F1/32;G06F1/28;G06F12/02;G11C11/00;G11C5/14 |
主分类号 |
G11C14/00 |
代理机构 |
Nixon Peabody LLP |
代理人 |
Nixon Peabody LLP ;Costellia Jeffrey L. |
主权项 |
1. A semiconductor device comprising:
a first circuit; a second circuit electrically connected to the first circuit; and a third circuit comprising:
a first register electrically connected to the second circuit, the first register comprising a first volatile memory unit and a first nonvolatile memory unit;a second register electrically connected to the second circuit, the second register comprising a second volatile memory unit and a second nonvolatile memory unit; and a fourth circuit electrically connected to the first circuit, the first register and the second register, wherein the first nonvolatile memory unit is configured to save a data from the first volatile memory unit during a data saving period, wherein the second circuit is configured to determine a length of the data saving period, wherein the fourth circuit is configured to send a first signal to the first circuit, and wherein the first circuit is configured to send a second signal to the second circuit to change the length of the data saving period on the basis of the first signal. |
地址 |
Kanagawa-ken JP |