发明名称 |
Method and algorithm for stabilizing the output state of an optical transceiver |
摘要 |
The invention relates to a method and algorithm for stabilizing the output state of an optical transceiver. The method includes comparing a signal quality monitor (SQM) register value with a predetermined threshold. If the SQM register value is less than or equal to the predetermined threshold, a microcontroller unit (MCU) reads and determines the rx_lol state bit value of a clock and data recovery (CDR) chip. If the rx_lol state bit value reaches a low logic level value at least 3 times, the MCU converts the state bit values of rx_lol and mod_nr into low logic level values, or else, convert the state bit values of rx_lol and mod_nr into high logic level values. If the SQM register value is greater than the predetermined threshold then the state bit values of rx_lol and mod_nr will be left unchanged. When there is no data input to the CDR chip, the method of the present invention will maintain rx_lol and mod_nr at high or low logic level values to stabilize the output state of the optical transceiver. |
申请公布号 |
US9059834(B2) |
申请公布日期 |
2015.06.16 |
申请号 |
US201213728788 |
申请日期 |
2012.12.27 |
申请人 |
Source Photonics, Inc. |
发明人 |
Zhou Xiaojun;Lu Meiling;Zheng Xiaoyi;Wan Jifeng |
分类号 |
H04B10/00;H04B10/06;H04L7/00;H04B10/079;H04B10/61;H04B10/43 |
主分类号 |
H04B10/00 |
代理机构 |
Central California IP Group, P.C. |
代理人 |
Fortney Andrew D.;Central California IP Group, P.C. |
主权项 |
1. A method for stabilizing an output state of an optical transceiver, comprising:
a) comparing a signal quality value from a clock data recovery (CDR) chip with a predetermined threshold; b) reading and deteimining a receiver loss of lock bit value of the CDR chip when the signal quality value is less than or equal to the predetermined threshold; c) converting the receiver loss of lock bit value and a module not ready bit value into a low logic value when the receiver loss of lock bit value of the CDR chip reaches a low logic value n times within a predetermined time; d) converting the receiver loss of lock bit value and the module not ready bit value into a high logic value when the receiver loss of lock bit value of the CDR chip does not reach the low logic value n times within the predetermined time; and e) leaving the receiver loss of lock bit value and the module not ready bit value unchanged when the signal quality value is greater than the predetermined threshold. |
地址 |
Chatsworth CA US |