Systems and methods for gate aware iterative data processing

摘要

The present inventions are related to systems and methods for iterative data processing scheduling. In one case a data processing system is disclosed that includes a data detector circuit and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The data decoder circuit is operable to repeatedly apply a data decoding algorithm to the detected output to yield a decoded output over a number of passes, where the number of passes is within an allowable number of local iterations selected based at least in part on a read gate signal.

主权项

1. A data processing system, the data processing system comprising:
a read gate signal operable to indicate reception of input data; a data detector circuit operable to apply a data detection algorithm to a data set to yield a detected output, wherein the data set is derived from a portion of the input data; and a data decoder circuit operable to repeatedly apply a data decoding algorithm to the detected output to yield a decoded output over a number of passes, wherein the number of passes is within an allowable number of local iterations selected based at least in part on the read gate signal.