发明名称 Method to form silicide contact in trenches
摘要 A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.
申请公布号 US9059096(B2) 申请公布日期 2015.06.16
申请号 US201213356090 申请日期 2012.01.23
申请人 International Business Machines Corporation 发明人 Guillorn Michael A.;Lavoie Christian;Shahidi Ghavam G.;Yang Bin;Zhang Zhen
分类号 H01L23/62;H01L21/285;H01L21/8238;H01L29/417;H01L29/66;H01L29/45;H01L29/786;H01L23/485;H01L21/768 主分类号 H01L23/62
代理机构 Fleit Gibbons Gutman Bongini & Bianco PL 代理人 Fleit Gibbons Gutman Bongini & Bianco PL ;Grzesik Thomas
主权项 1. A transistor comprising: a dielectric layer formed on a first semiconductor layer, a gate spacer, and a gate stack, wherein the gate spacer and gate stack are formed on the first semiconductor layer, and wherein the dielectric layer extends at least to a top surface of the gate stack, wherein the first semiconductor layer is planar and a bottom portion of the gate stack is formed in contact with a top surface of the first semiconductor layer; source/drain regions formed within the first semiconductor layer, where the source/drain regions are adjacent to and in contact with shallow trench isolation structures, and wherein a top surface of the source/drain regions and the top surface of the first semiconductor layer are coplanar; source/drain extensions formed beneath the gate spacer, and adjacent to and in contact with the source/drain regions, respectively, where a top surface the source/drain extensions is planar with a top surface of the shallow trench isolation structures and a top surface of the source/drain regions; a first contact trench and a second contact trench formed on and above at least a portion of the source/drain regions, respectively, wherein the dielectric layer comprises vertical sidewalls within each of the first contact trench and the second contact trench; wherein each of the first contact trench and second contact trench comprises: a second semiconductor layer conformally formed within each of the first contact trench and the second contact trench, wherein the second semiconductor layer comprises a single layer of semiconductor material, and wherein a bottom portion of the second semiconductor layer is formed in contact with exposed portions of the first semiconductor layer comprising the source/drain regions, respectively, and wherein the second semiconductor layer comprises vertical sidewalls conformally formed in contact with the vertical sidewalls of the dielectric layer in their entirety within the respective first contact trench and a second contact trench, wherein the bottom portion and vertical sidewalls of the second semiconductor layer comprise the same semiconductor material;a metallic layer formed in contact with and conformal to the second semiconductor layer;a conductive contact liner formed in contact with and conformal to the metallic layer;a conductive contact layer formed in contact with and conformal to the conductive contact liner and filling a space between inner vertical sidewalls of the conductive contact liner; andone of a silicide region and a germanide region formed from the second semiconductor layer and the metallic layer and formed between the metallic layer and the conductive contact liner.
地址 Armonk NY US