Structure and method to obtain EOT scaled dielectric stacks

摘要

Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

主权项

1. A method of forming a semiconductor structure comprising: incorporating at least one high k material dopant element within an interfacial layer of at least one patterned gate stack including a high k gate dielectric, a metallic electrode and a Si-containing electrode, wherein said incorporating modifies the interfacial layer into a modified interfacial layer comprising a reaction product of a material of the interfacial layer and at least said at least one high k material dopant element, said modified interfacial layer has an oxygen content that is less than an oxygen content of said interface layer, and wherein said incorporating said at least one high k material dopant element includes diffusion of said high k material dopant element from an overlying interfacial scaling material layer.