Method of detecting transistors mismatch in a SRAM cell

摘要

The present invention provides a method of detecting the transistor mismatch in a SRAM cell. The SRAM cell comprises two pass-gate transistors and a bi-stable circuit including two pull up transistors and two pull down transistors. The method comprises: providing two measuring transistors, whose gates are connected to a second word line, sources are connected to the outputs of the bi-stable circuit respectively and drains are connected to two measuring terminals respectively; turning on the measuring transistors and turning off the pass-gate transistors; detecting the voltage-current curve of the two pull down transistors and the two pull up transistors through the measuring transistors at the measuring terminals so as to detect the transistor mismatch in the SRAM cell.

主权项

1. A method of detecting the transistor mismatch in a SRAM cell, wherein the SRAM cell comprises a first and a second pass-gate transistors (PG1, PG2), and a bi-stable circuit which includes a first and a second pull up transistors (PU1, PU2) and a first and a second pull down transistors (PD1, PD2); wherein, the gate electrodes of the first and the second pass-gate transistors are connected to a first word line (WLA), the source electrodes thereof are connected to the outputs of the bi-stable circuit respectively, and the drain electrodes thereof are connected to a first and a second bit line (BL, BL) respectively; the method comprises:
step a, providing a first and a second measuring transistors (PM1, PM2), the gate electrodes of the first and second measuring transistors (PM1, PM2) are connected to a second word line (WLB), the source electrodes thereof are connected to the outputs of the bi-stable circuit respectively, and the drain electrodes thereof are connected to a first and second measuring terminals ( BLM, BLM) respectively; step b, enabling the second word line (WLB) and disabling the first word line (WLA); step c, determining the value of the data stored in the SRAM cell, if the data is “0”, turning to step d1; and if the data is 1, turning to step d2; step d1, detecting the voltage-current curves of the first pull down transistor (PD1) and the second pull up transistor (PU2) at the first and second measuring terminals ( BLM, BLM) respectively, turning to step e; step d2, detecting the voltage-current curves of the first pull up transistor (PU1) and the second pull down transistor (PD2) at the first and second measuring terminal ( BLM, BLM) respectively, turning to step e; step e, determining whether the voltage-current curves of the first and second pull down transistors (PD1, PD2) and the first and second pull up transistors (PU1, PU2) are all detected, if no, turning to step f; if yes, turning to step g; step f, enabling the first word line (WLA) and disabling the second word line (WLB), and writing a complementary data into the SRAM cell and turning to step a; step g, determining the transistor mismatch according to the voltage-current curves of the first and second pull down transistors (PD1, PD2) and the first and second pull up transistors (PU1, PU2).