| 发明名称 |
Power management SRAM write bit line drive circuit |
| 摘要 |
A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage. |
| 申请公布号 |
US9058861(B2) |
申请公布日期 |
2015.06.16 |
| 申请号 |
US201213718657 |
申请日期 |
2012.12.18 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Behrends Derick G.;Christensen Todd A.;Hebig Travis R.;Launsbach Michael |
| 分类号 |
G11C7/00;G11C7/12;G11C11/419 |
主分类号 |
G11C7/00 |
| 代理机构 |
|
代理人 |
Williams Robert R. |
| 主权项 |
1. A static random access memory (SRAM) comprising:
two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC); a write driver logic coupled to the WBL and the WBLC, the write driver logic adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel; the write driver logic further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, wherein the downlevel is a voltage suitable to be interpreted as a downlevel on the WBLC by two or more SRAM cells. |
| 地址 |
Armonk NY US |
