Pad selection in memory devices configured for stacked arrangements

摘要

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

主权项

1. A semiconductor memory device, comprising:
a plurality of pads allocated to a data input/output (DQ) signal on the semiconductor memory device; a stack position identifier configured to identify a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices; and a pad selector configured to select one of the plurality of pads to be connected to the DQ signal on the semiconductor memory device in response to the stack position identifier, wherein the pad selector is further configured to disconnect each of a remaining of the plurality of pads from the DQ signal based on the stack position identifier.