Structure and method of forming enhanced array device isolation for implanted plate EDRAM

摘要

A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

主权项

1. A memory device comprising:
a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is entirely located above a topmost surface of a second semiconductor layer; a capacitor present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer and the capacitor includes a bottom electrode having a surface in direct physical contact with a bottommost surface of the buried dielectric layer, wherein a protective oxide is present in a void that lies adjacent the first semiconductor layer, said protective oxide having a topmost surface that is coplanar with a topmost surface of said first semiconductor layer, a bottommost surface that is in direct physical contact with a topmost surface of said buried dielectric layer and a sidewall surface that is in directly physical contact with a sidewall surface of said first semiconductor material; and a pass transistor present atop the semiconductor on insulator substrate in electrical communication with the capacitor; wherein said protective oxide is present only on one side of the trench, and wherein a doped polysilicon region is present on another side of the trench; and wherein a top trench oxide is positioned between said protective oxide and said doped polysilicon region.