Metal-oxide-semiconductor (MOS) device and method for fabricating the same

摘要

A Metal-Oxide-Semiconductor (MOS) device is disclosed. The MOS device includes a substrate, a well region formed in the substrate, and a gate located on the substrate. The MOS device also includes a first lightly-doped region arranged in the well region at a first side of the gate and overlapping with the gate, and a second lightly-doped region arranged in the well region at a second side of the gate and overlapping with the gate. Further, the MOS device includes a first heavily-doped region formed in the first lightly-doped region, and a second heavily-doped region formed in the second lightly-doped region. The MOS device also includes a first high-low-voltage gate oxide boundary arranged between the first heavily-doped region and the gate, and a second high-low-voltage gate oxide boundary arranged between the second heavily-doped region and the gate. The gate covers the first high-low-voltage gate oxide boundary and the second high-low-voltage gate oxide boundary at the first side and the second side of the gate, respectively.

主权项

1. A Metal-Oxide-Semiconductor (MOS) device, comprising:
a substrate; a well region formed in the substrate; a gate located on the substrate; a first lightly-doped region arranged in the well region at a first side of the gate and overlapping with the gate; a second lightly-doped region arranged in the well region at a second side of the gate and overlapping with the gate; a first heavily-doped region formed in the first lightly-doped region; a second heavily-doped region formed in the second lightly-doped region; a first high-low-voltage gate oxide boundary arranged between the first heavily-doped region and the gate; and a second high-low-voltage gate oxide boundary arranged between the second heavily-doped region and the gate, wherein the first high-low-voltage gate oxide boundary includes a nitride layer and a buffer oxide layer, aligned sequentially above the first heavily-doped region at the first side of the gate, and the first high-low-voltage gate oxide boundary is located below the gate and a gate sidewall at the first side of the gate and has an outer edge aligned with or within an outer edge of the gate sidewall without taking extra space of the MOS device; and wherein the second high-low-voltage gate oxide boundary includes a nitride layer and a buffer oxide layer, aligned sequentially above the second heavily-doped region at the second side of the gate, and the second high-low-voltage gate oxide boundary is located below the gate and the gate sidewall at the second side of the gate, and has an outer edge aligned with or within an outer edge of the gate sidewall without taking extra space of the MOS device.