Frequency determination across an interface of a data processing system

摘要

One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit configured to be coupled to an interconnect of a multiprocessor system and configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.

主权项

1. An interface of a processor unit configured to be coupled to an interconnect of a multiple processor system and configured such that:
a first portion of the interface provides a signal to a second portion of the interface, wherein the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a frequency of a cache of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface, after the second portion of the interface circulates the signal; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal, after the first portion of the interface receives the signal from the second portion of the interface; and the interface provides information indicating the cache command rate to the interconnect.