发明名称 Solid-state imaging device, method of driving a solid-state imaging device, and electronic apparatus including a solid-state imaging device
摘要 A solid-state imaging device includes a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels.
申请公布号 US9060143(B2) 申请公布日期 2015.06.16
申请号 US201414475286 申请日期 2014.09.02
申请人 SONY CORPORATION 发明人 Honda Katsumi;Takatsuka Takafumi
分类号 H04N3/14;H04N9/04;H04N5/363;H04N5/225;H04N5/335;H04N5/374;H04N5/376;H01L27/146 主分类号 H04N3/14
代理机构 Sheridan Ross P.C. 代理人 Sheridan Ross P.C.
主权项 1. A solid-state imaging device, comprising: a first chip including a cyclic layout pattern circuit having unit circuits cyclically arranged in a regular pattern in at least one of a row direction along which rows of pixels of a pixel array having a matrix of rows and columns of pixels, each pixel including a photoelectric converter, are arranged, and a column direction along which columns of pixels of the pixel array are arranged; a second chip laminated on the first chip, the second chip including an adjustment circuit for adjusting individually a timing of a signal of each unit circuit of the cyclic layout pattern circuit, the adjustment circuit including a storage unit and a plurality of unit circuits corresponding to the unit circuits of the cyclic layout pattern circuit; and a connection unit, having a three-dimensional connection structure, for electrically connecting each unit circuit of the cyclic layout pattern on the first chip to each unit circuit of the adjustment circuit on the second chip in a mapped relationship.
地址 JP