| 摘要 |
A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each coupled to a column of memory cells. Sense amplifiers are selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines. A voltage supply having a voltage VBL corresponding to a bitline precharge voltage is selectively connectable to each bitline. Logic selectively connects each bitline and the complementary bitline to one of a sense amplifier and the voltage supply during a read operation. Each bitline connected to the sense amplifier is adjacent to a bitline concurrently connected to the voltage supply. A method is also described. |
