MEMORY DEVICE WITH DEFINED PROGRAMMING TRANSACTION TIME

摘要

This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.

主权项

1. A memory device, comprising:
memory cells in a memory array; logic to hold a received value representing a programmably-defined memory transaction time, defined according to a calibration operation performed on memory cells of the memory array, the programmably-defined memory transaction time corresponding to a maximum time expected for correct programming of data into memory cells of the memory array; and logic to compare the programmably-defined memory transaction time with time consumed by a write operation in the memory array, and to generate a signal state for provision to a memory controller, wherein the signal state indicates whether the write operation has resulted in correct programming of data into memory cells of the memory array within the programmably-defined memory transaction time.