DYNAMIC SWITCH SCALING FOR SWITCHED-MODE POWER CONVERTERS

摘要

Techniques for optimizing the trade-off between minimizing switching losses and minimizing conduction losses in a buck converter. In an aspect, each of a high-side switch and a low-side switch may be implemented as a plurality of parallel-coupled transistors, each transistor having an independently controllable gate voltage, allowing adjustment of the effective transistor size. In response to the target voltage of the buck converter corresponding to a relatively high voltage range, more high-side switch transistors and fewer low-side switch transistors may be selected. Similarly, in response to the target voltage corresponding to a relatively low voltage range, more low-side switch transistors and fewer high-side switch transistors may be selected. In an aspect, the techniques may be applied during a pulse-frequency modulation mode.

主权项

1. An apparatus comprising:
a plurality of parallel-coupled PMOS transistors that couple a source voltage to an inductor; a plurality of parallel-coupled NMOS transistors that couple the inductor to ground, wherein the inductor is coupled to an output voltage that is driven to a target output voltage; and a control logic block that generates a plurality of gate control voltages that control each of the plurality of parallel-coupled PMOS transistors and the plurality of parallel-coupled NMOS transistors, wherein in response to the target output voltage being adjusted, the control logic block adjusts a quantity of the plurality of parallel-coupled PMOS transistors and the plurality of parallel-coupled NMOS transistors that are selectively enabled.