Digital Signal Processing Data Transfer

摘要

A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

主权项

1. A digital signal processing system, comprising:
a memory device; a memory access controller providing a plurality of channels for accessing the memory device; a plurality of fixed function accelerators, each arranged to only perform a predefined specialised signal processing task and not being capable of changing the task performed, each connected to the memory access controller and each configured to read data from the memory device via one of the channels, perform one or more operations on the data, and write data to the memory device via one of the channels; and a multi-threaded processor coupled to the memory access controller and configured to execute a plurality of threads, each thread arranged to control one of the channels, wherein at least one of the threads is configured to detect an occurrence of an event and, responsive thereto, control provision of data from the memory device to a selected fixed function accelerator using the thread's associated channel.