DYNAMIC CASCODE-MANAGED HIGH-VOLTAGE WORD-LINE DRIVER CIRCUIT

摘要

A method of operation of a high-voltage word-line driver circuit for a memory device prevents any single transistor of the driver from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

主权项

1. A method of operation of a dynamic logic driver circuit, the method comprising:
receiving an input logic signal; pre-charging an evaluation node of the dynamic driver circuit with a first one of a plurality of transistors forming an input logic stack having source and drain terminals connected in series between a power supply voltage and a power supply return voltage; evaluating the input logic signal with the input logic stack by providing the input logic signal to a gate of a second one of the plurality of transistors and selectively discharging the evaluation node in response to a first state of the input logic signal; first preventing failure of a given one of the first transistor or the second transistor by biasing a third one of the first plurality of transistors with a first reference voltage between the power supply voltage and the power supply return voltage, so that the third transistor forms a cascode follower that prevents a leakage current within the input logic stack from causing a full difference between the power supply voltage and the power supply return voltage from being applied across a given one of the first transistor or the second transistor; and generating a buffered output signal from a state of the evaluation node, wherein a first voltage swing of the buffered output signal is substantially greater than a second voltage swing of the input logic signal.