SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

摘要

A successive approximation register (SAR-ADC) including a digital-to-analog conversion (DAC) circuit, a sample-and-hold circuit, a comparison circuit and a SAR logic control circuit is provided. The DAC circuit is configured to convert an N-bits digital logic signal into a comparison signal, where N is a positive integer. The sample-and-hold circuit is configured to sample and hold an analog input signal. The comparison circuit is configured to use the analog input signal held by the sample-and-hold circuit as a basis for comparing with the comparison signal and thereby generates a comparison result signal. The SAR logic control circuit is configured to provide the N-bits digital logic signal and determine a logic state of each of bits of the digital logic signal one by one according to the comparison result signal, and thus generate a digital output signal related to the analog input signal.

主权项

1. A successive approximation register analog-to-digital converter, comprising:
a digital-to-analog conversion circuit, configured to convert an N-bits digital logic signal into a comparison signal in analog form, wherein N is a positive integer; a sample-and-hold circuit, configured to sample and hold an analog input signal; a comparison circuit, coupled to the digital-to-analog conversion circuit and the sample-and-hold circuit, and configured to use the analog input signal held by the sample-and-hold circuit as a basis for comparing with the comparison signal and thereby generate a comparison result signal; and a successive approximation register logic control circuit, configured to provide the N-bits digital logic signal and determine a logic state of each of bits of the digital logic signal one by one according to the comparison result signal, so as to generate a digital output signal related to the analog input signal.