| 发明名称 |
DIGITAL OUTPUT CLOCK GENERATION |
| 摘要 |
An on-chip clock signal generation apparatus is provided which is configured to generate an output clock signal to be passed off-chip in association with an output data signal. The apparatus comprises: an input configured to receive an input clock signal and clock phase generation circuitry configured to generate a plurality of candidate clock signals in dependence on the input clock signal. The candidate clock signals are phase-shifted with respect to one another. Selection circuitry is configured to select and output one of the candidate clock signals as the output clock signal in dependence on at least one selection signal. All components of the apparatus are embodied as digital components. |
| 申请公布号 |
US2015162918(A1) |
申请公布日期 |
2015.06.11 |
| 申请号 |
US201314097963 |
申请日期 |
2013.12.05 |
| 申请人 |
ARM Limited |
发明人 |
SWAMY Ramnath Bommu Subbiah |
| 分类号 |
H03L7/081;H03L7/083 |
主分类号 |
H03L7/081 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An on-chip clock signal generation apparatus configured to generate an output clock signal to be passed off-chip in association with an output data signal, the apparatus comprising:
an input configured to receive an input clock signal; clock phase generation circuitry configured to generate a plurality of candidate clock signals in dependence on the input clock signal, wherein the candidate clock signals are phase-shifted with respect to one another; and selection circuitry configured to select and output one of the candidate clock signals as the output clock signal in dependence on at least one selection signal, wherein all components of the apparatus are embodied as digital components. |
| 地址 |
Cambridge GB |
