FRACTIONAL-N SPREAD SPECTRUM STATE MACHINE

摘要

Embodiments of the present invention may be realized in a fractional-N spread spectrum clock (SSC) generator utilizing an SSC state machine generating a single clock gating signal to drive a fractional-N phase locked loop (PLL) frequency multiplier to generate an SSC output clock. The SSC generator leverages upon the development of the digital PLL to implement the SSC generator within the final core PLL. The SSC generator only requires a relatively low base frequency reference clock and digital programming including an SSC rate and a modulation definition signal to produce the fractional-N spread spectrum output clock. The SSC generator results in cost savings through a high frequency SSC output clock generator that utilizes a relatively slow reference clock without the need for multiple high frequency clocks or multiple feedback clocks to drive the PLL.

主权项

1. A fractional-N spread spectrum clock (SSC) generator for a computer system, comprising:
a fractional-N phase locked loop frequency multiplier (PLL) configured to receive a reference clock signal as an input and applying a variable multiplication factor to the reference clock signal to produce an output clock signal having a variable output frequency; and a spread spectrum clock (SSC) state machine configured to produce a single clock gating signal fed into the PLL for controlling the multiplication factor of the PLL to vary the output clock signal of the PLL; wherein the multiplication factor is set to a nominal value N and the single clock gating signal defines a modulation waveform that drives the variable multiplication factor to cause the PLL the generate a fractional-N spread spectrum output clock signal defined by digital programming input to the SSC state machine; and wherein the digital programming input to the SSC state machine comprises a modulation definition signal and an SSC rate signal.