| 摘要 |
<p>The present invention is to reduce parasitic capacitance generated in an intersection region (60) where the gate line (G) of an active matrix type display device (1) interests with the data line (D). The intersection region includes a substrate (10), a date line (D) formed on the substrate, a first insulating layer (61) formed on the data line, a gate line (G) which is formed on the first insulating layer and has a gate line cutting part (62) which has a cut part corresponding to the data line, a second insulating layer (66) formed on the upper part of the gate line cutting part (62), and a gate line connection part (64) which is formed in the upper part of the second insulating layer and is electrically connected to both ends of the cut gate line in the gate line cutting part.</p> |
