| 摘要 |
A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time. |
| 主权项 |
1. A phase locked loop (PLL), comprising:
a voltage controlled oscillator (VCO) configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal, the second oscillating signal being an inverted version of the first oscillating signal, the first and second oscillating signals having a predetermined VCO period (TVCO); a loop filter configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter; and a first feedback control unit having a first feedback control output node coupled to the input node of the loop filter, the first feedback control unit being configured to
apply a first predetermined amount of current (ICP1), along a first current direction, to the first feedback control output node during a variable period of time, the variable period of time being defined by a reference signal, the first oscillating signal, and the second oscillating signal, the reference signal having a predetermined reference period (TREF), a predetermined ratio of TREF to TVCO being (N+f), N being a positive integer, and f being a fraction; andapply one of K second predetermined amounts of current (ICP2[0:K−1]), along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time, the K second predetermined amounts of current being selected in a sequential and repetitive manner, K being a positive integer, and (K·f) being an integer. |
