Method of Designing Semiconductor Device, Designing Assistance Program, Designing Apparatus, and Semiconductor Device

摘要

The present invention provides a method of designing a semiconductor device capable of executing a DVFS control which minimizes consumption energy. A consumption power profile P(t) when a known operating voltage and a clock of a known frequency are given to a logic circuit as a DVFS target and a process as a DVFS target is executed is obtained. The obtained power profile is converted to a function related to a clock cycle q(t), and a load capacity of the target logic circuit is obtained as a function of the clock cycle q(t). An operating voltage and an operating frequency are calculated as functions (V(q), f(q)) for a clock cycle so as to satisfy a condition using, as a constant, a product (C(q)·(dq/dt){circle around ( )}3) of the load capacity function and cube of time differentiation of the clock cycle. The calculated functions of the operating voltage and the operating frequency are solutions of the Euler equation according to the calculus of variations, and consumption energy is minimized.

主权项

1. A method of designing a semiconductor device, by executing a designing assistance program by a computer, for a logic circuit to which an operating voltage and an operating frequency are given and which executes a predetermined process synchronously with a clock signal, the method for calculating an operating voltage and an operating frequency of the logic circuit in a period in which the process is executed, comprising the steps of:
providing, as a power profile, a relation of consumption power to a clock cycle accompanying execution of the process when the process is executed by giving a first operating voltage and a first operating frequency to the logic circuit; obtaining, as a load capacity function, a function of load capacity of the logic circuit, for the clock cycle accompanying execution of the process on the basis of the power profile; and calculating, each as a function for the clock cycle, the operating voltage and the operating frequency of the logic circuit in the period in which the process is executed so as to satisfy an Euler equation with respect to power and a clock cycle on the basis of the load capacity function.