| 发明名称 |
DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT |
| 摘要 |
An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer. |
| 申请公布号 |
US2015162273(A1) |
申请公布日期 |
2015.06.11 |
| 申请号 |
US201314102623 |
申请日期 |
2013.12.11 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIAO Hung-Jen;CHEN Jung-Hsuan;TIEN Chien Chi;WU Ching-Wei;TSAI Jui-Che;CHENG Hong-Chen;WANG Chung-Hsing |
| 分类号 |
H01L23/498;H01L27/11 |
主分类号 |
H01L23/498 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An integrated circuit (IC) memory device, comprising:
a first conductive layer; a second conductive layer separated from the first conductive layer, the second conductive layer formed over the first conductive layer; at least one double exposure and double etch (2P2E) pin box formed in and electrically coupled to the first conductive layer; and at least one single exposure and single etch (1P1E) pin box formed in and electrically coupled to the second conductive layer. |
| 地址 |
Hsinchu TW |
