Dual-Gated Group III-V Merged Transistor

摘要

There are disclosed herein various implementations of a group III-V merged cascode transistor. Such a group III-V merged cascode transistor includes a group III-V body disposed over a substrate and configured to produce a two-dimensional electron gas (2DEG). The group III-V body includes a group III-V barrier layer situated over a group III-V channel layer, and a source electrode and a drain electrode. The group III-V merged cascode transistor also includes an enable gate disposed in a recess extending substantially through the group III-V barrier layer, and an operational gate disposed over the group III-V barrier layer, the operational gate not being in physical contact with the enable gate.

主权项

1. A group III-V merged cascode transistor comprising:
a group III-V body disposed over a substrate and configured to produce a two-dimensional electron gas (2DEG), said group III-V body including a group III-V barrier layer situated over a group III-V channel layer; a source electrode and a drain electrode; an enable gate disposed in a recess extending substantially through said group III-V barrier layer, and an operational gate disposed over said group III-V barrier layer, said operational gate not being in physical contact with said enable gate.