| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of: reducing time which is elapsed from a transition from a power-on and a transition from a reference frequency signal discontinuation to the presence of the reference frequency signal input, and is elapsed before a lock; stabilizing oscillation during the lock; and allowing for quick stabilization from the lock to the vicinity of the center of a control voltage when changed from a locked state to the reference frequency signal discontinuation. <P>SOLUTION: During power-on, and when changed from an REF discontinuation state to the presence of REF, a gain of an operational amplifier 39 in an integrator 15 is increased, and a gain of an operational amplifier 37 in an amplifier 16 is increased, thereby reducing the time elapsed before a lock. The gain of the operational amplifier 37 in the amplifier 16 is decreased during the lock, and the gain of the operational amplifier 39 in the integrator 15 is decreased when the REF discontinuation occurs in a locked state. Therefore, a PLL circuit can advance discharge of an electrical charge of a capacitor 28 during free running, and can reduce time required for a transition to a free running frequency, thereby advancing stabilization. <P>COPYRIGHT: (C)2013,JPO&INPIT |
