| 摘要 |
<p>A memory array having a smaller active area pitch is provided. In accordance with embodiments of the present invention, active regions are formed in a substrate and transistors are formed between adjacent active regions such that the active regions form the source/drain regions of the transistors. Word lines are formed perpendicular to the active regions and are electrically coupled to the gates of the transistors. Bit lines may be formed over the active regions to provide electrical contacts to the source/drain regions. In an embodiment, the word lines may be formed of poly-silicon over a layer of dielectric material formed over the transistors. In this embodiment, the bit lines may be formed on the metal layers. The word lines and dielectric layer may have a planar or non-planar surface.</p> |
