| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an HPF or the like using an SC circuit, capable of reducing an area when raising the clock frequency of a switch configuring the SC circuit, and capable of lowering a cutoff frequency without losing design flexibility. <P>SOLUTION: The high pass filter 10 of M (M is an integer of≥2) order using the switched capacitor circuit includes a first switched capacitor integrator 100<SB>1</SB>having a first operational amplifier OP1 provided with a first input end, a second input end and an output end and a first input capacitor C1. To the first input end, the input signal V<SB>IN</SB>of the high pass filter 10 is supplied. To the second input end, a feedback signal fed back from the output end is supplied through the first input capacitor C1. From the output end, the output signal V<SB>OUT</SB>of the high pass filter 10 is output. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
