发明名称 半導体装置の製造方法
摘要 <p><P>PROBLEM TO BE SOLVED: To inhibit both roughening and black silicon of a trench sidewall in a manufacturing method of a vertical MOSFET having parallel pn regions formed by a trench refill method when etching deep trenches at a trench aperture ratio of 30% and over. <P>SOLUTION: In a process of forming a plurality of trenches in a semiconductor substrate, an etching gas containing oxygen and at least sulfur hexafluoride is used, where a flow rate of the oxygen is set at approximately 0.8 times or more and 2.0 times or less than a flow rate of the sulfur hexafluoride, or preferably nearly equal flow rate. Accordingly, a deposition amount of an etching product on a trench sidewall can be controlled and roughening of the trench sidewall and generation of black silicon in etching can be inhibited at the same time. <P>COPYRIGHT: (C)2012,JPO&INPIT</p>
申请公布号 JP5731427(B2) 申请公布日期 2015.06.10
申请号 JP20120042760 申请日期 2012.02.29
申请人 发明人
分类号 H01L21/336;H01L21/3065;H01L29/78 主分类号 H01L21/336
代理机构 代理人
主权项
地址