Field programmable gate array utilizing two-terminal non-volatile memory

摘要

Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

主权项

1. A method of operating a field programmable gate array (FPGA), comprising:
initiating an active mode for the FPGA; applying a read voltage to a programmable two-terminal resistive memory element of a configuration cell of the FPGA; applying electrical ground to a second programmable two-terminal resistive memory element of the configuration cell of the FPGA; and deactivating a programming circuit of the configuration cell, and floating an output of the programming circuit that is connected exclusively to a common node shared by the programmable two-terminal resistive memory element and the second programmable two-terminal resistive memory element.