Semiconductor device performing stress test

摘要

A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.

主权项

1. A semiconductor device comprising:
a memory cell array divided into a plurality of memory cell mats by an intervention of a plurality of sense amplifier arrays, each of the memory cell mats having a plurality of word lines; and a test circuit performing a test operation that selects ones of the plurality of word lines at one time each included in selected ones of the plurality of memory cell mats that are not disposed adjacent to each other, wherein each of the sense amplifier arrays includes a plurality of sense amplifiers each connected to an associated pair of bit lines, one of the pair of bit lines is arranged in one of two memory cell mats adjacent to each other, and other of the pair of bit lines is arranged in other of the two memory cell mats.