发明名称 |
Hardware computing system with extended calculation and method of operation thereof |
摘要 |
A method of operation of a hardware computing system includes: receiving a command stream from a general purpose central processing unit; transferring a command from the command stream by an application manager; activating a programmable execution array, by the application manager, for processing the command; and providing a response through a result stateful multiplexer to the general purpose central processing unit for the command from the command stream. |
申请公布号 |
US9055070(B2) |
申请公布日期 |
2015.06.09 |
申请号 |
US201313789649 |
申请日期 |
2013.03.07 |
申请人 |
Xcelemor, Inc. |
发明人 |
Zievers Peter J. |
分类号 |
G06F3/00;G06F9/44;G06F9/46;G06F13/00;G05B13/00;G06F17/00;H04L29/08;G06F9/54 |
主分类号 |
G06F3/00 |
代理机构 |
Ishimaru & Associates LLP |
代理人 |
Ishimaru & Associates LLP |
主权项 |
1. A method of operation of a hardware computing system comprising:
receiving a command stream from a general purpose central processing unit; transferring a command from the command stream by an application manager; activating a programmable execution array, by the application manager, for processing the command includes:
monitoring a memory bus for receiving the command,verifying, by a command processor, a configuration of the programmable execution array,identifying an execution cell within the programmable execution array for executing the command, andtransferring, by a field programmable gate array (FPGA) interface module, input parameters for the command to the execution cell; and providing a response through a result stateful multiplexer to the general purpose central processing unit for the command from the command stream. |
地址 |
Livermore CA US |