Packet switch based logic replication

摘要

A method for debugging comprising configuring a switching logic mapping source subchannels to destination subchannels, as virtual channels to forward the packets from the source subchannels to the destination subchannels. The method further comprising configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronously with the plurality of clock domains with the delay period.

主权项

1. A method for debugging a source circuit, the method comprising upon receiving information regarding the source circuit:
compiling representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains, each source subchannel to generate packets carrying signal data from one of the portions of the source logic; compiling representation of a destination circuit including one or more destination subchannels associated with portions of destination logic replicating the source logic, each destination subchannel to forward the signal data via the packets to one of the portions of the destination logic; configuring a switching logic mapping the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels, the packets based on a packet format including a header field and a payload field, the header field to carry channel identifiers identifying the virtual channels and the payload field to carry the signal data; and configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronous with the plurality of clock domains with the delay period.