| 发明名称 |
Method and apparatus for supporting a unified debug environment |
| 摘要 |
A field programmable gate array (FPGA) includes a soft processor and a soft processor debug unit implemented by programmable logic on the FPGA. The FPGA includes a system on a chip (SOC) that includes a hard processor and a hard processor debug unit. The FPGA includes a bus bridge, coupled to an input output (IO) of the FPGA, operable to transmit data between the IO and the soft processor debug unit and the hard processor debug unit. |
| 申请公布号 |
US9053232(B2) |
申请公布日期 |
2015.06.09 |
| 申请号 |
US201213715161 |
申请日期 |
2012.12.14 |
| 申请人 |
Altera Corporation |
发明人 |
Ahmed Muhammad;Reghunath Manoj |
| 分类号 |
G06F11/00;G06F11/36;G06F11/27 |
主分类号 |
G06F11/00 |
| 代理机构 |
|
代理人 |
Cho L. |
| 主权项 |
1. A hybrid field programmable gate array (FPGA), comprising
a soft processor and a soft processor debug unit implemented by programmable logic on the FPGA; a system on a chip (SOC) that includes a hard processor and a hard processor debug unit; and a bus bridge, coupled to an input output (IO) of the FPGA, that transmits data between the IO and the soft processor debug unit and the hard processor debug unit. |
| 地址 |
San Jose CA US |
