发明名称 Delay locked loop and semiconductor apparatus
摘要 A delay locked loop includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal; a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal; a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code; and a delay code generation unit configured to control the delay code in response to the calculation code.
申请公布号 US9054715(B2) 申请公布日期 2015.06.09
申请号 US201313845270 申请日期 2013.03.18
申请人 SK Hynix Inc. 发明人 Kim Kwan Dong
分类号 H03L7/06;H03L7/081;H03L7/085;H03L7/097 主分类号 H03L7/06
代理机构 William Park & Associates Ltd. 代理人 William Park & Associates Ltd.
主权项 1. A delay locked loop comprising: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal; a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal; a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code; and a delay code generation unit configured to control the delay code in response to the calculation code, wherein the calculation code generation unit comprises: a first converter configured to receive the reference clock signal and the feedback clock signal and generate the phases of the reference clock signal as the first code; a second converter configured to receive the reference clock signal and the feedback clock signal and generate the phase of the feedback clock signal as the second code; and a calculator configured to calculate a difference between the first and second codes and generate the calculation code.
地址 Gyeonggi-do KR