Embedded NVM in a HKMG process

摘要

A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

主权项

1. A semiconductor fabrication process comprising:
providing a wafer comprising;
a plurality of nonvolatile memory cell gate structures formed over a substrate with one or more polysilicon layers, anda plurality of sacrificial transistor gate structures formed over the substrate with the one or more polysilicon layers; forming a dielectric layer having a substantially flat upper surface which exposes an upper surface of the plurality of sacrificial transistor gate structures; forming a protective mask layer over the plurality of nonvolatile memory cell gate structures; selectively removing the plurality of sacrificial transistor gate structures using the protective mask layer to protect the plurality of nonvolatile memory cell gate structures to form a plurality of gate electrode openings in the dielectric layer without removing the plurality of nonvolatile memory cell gate structures; forming a metal layer in the plurality of gate electrode openings; and polishing the metal layer down to be substantially coplanar with the plurality of nonvolatile memory cell gate structures to define a plurality of high-k metal gate electrodes in the plurality of gate electrode openings.